1. Field of the Invention
This invention is related to a method of designing logical circuits. More specifically, it is related to a logical simulation system which simulates the action of a logical circuit, and a method of changing the logic in a logical simulation system.
2. Description of the Prior Art
In recent years devices made up of logical circuits such as digital computers have been becoming larger in scale and more complicated, and logical simulation has been becoming increasingly important in testing the design of those devices. In addition, as the devices become larger in scale, there is a demand for the logical simulation to become faster; for this reason, specialized hardware has been developed for the purpose of simulating large scale circuits at high speed.
By using this hardware, the simulation has become faster, but as before it remains necessary to produce the simulation model itself on a general purpose computer, raising the problem that the time required to create the model increases. In particular, when part of a logical circuit is modified, it is usual for the contents of the logical data base in which the logical circuit data are stored to be changed, meaning that the simulation model must be recreated.
FIG. 1 shows the concept of a conventional conversational type simulation. The designer first creates data base for the logical circuit which is to be the object of the simulation; then the computer models that data base to create the simulation model. Then the computer executes the simulation model while conversing with the designer. When a circuit is modified, the designer must re-input part of the data base.
FIG. 2 is a flow chart of the conventional conversational type simulation. In FIG. 2, the designer first investigates whether or not there is an error in the circuit (step ST1); if an error is discovered, that fact is input into the computer. The computer inquires of the designer whether or not to execute the simulation (step ST2); if the answer is YES, the simulation is executed(step ST3). Then, if there is an instruction to end the simulation (step ST4, YES), the processing is ended.
If an error is not discovered in step ST1, then the processing in step ST3 and subsequent steps is performed; if it does not end with step ST4, then the processing is repeated starting with step ST1. Also, if it is desired to modify the location in the circuit where the error was discovered, the designer answers NO in step ST2 and YES in step ST4 to temporarily halt the simulation. Then part of the data base is changed, the conversational type simulation is restarted and the simulation model is recreated.
In this method, as the scale of the circuit becomes larger, the time required to recreate the model increases, and the turnaround time required to make a logical correction and check the result by repeating the simulation becomes longer.
One method that has been available to solve this kind of problem is that when a simulation model that has been created is partially modified, only the hierarchical block containing the part that has been modified is recompiled and then linked to the other parts, thus shortening the processing time. However, even in this method considerable time is required to recompile the hierarchical block and link it to the other parts, and in the case of a large system the processing time is not sufficiently shortened. In addition, it is necessary for the simulation model to contain hierarchical information, producing the problem that the model becomes more complicated as the scale of the file becomes larger. Also, if an error that has been discovered in the simulation is to be corrected, it is generally desired to modify the contents of the logical data base after a tentative correction has been made and normal operation confirmed by means of a simulation. That is to say, since the logical data base is master information for performing unified management of the design information and has a file that several designers will refer to, it is better that the change is made after the appropriateness of the logic has been confirmed.